Bronis de Supinski

Bronis R. de Supinski is the Chief Technology Officer (CTO) for Livermore Computing (LC) at Lawrence Livermore National Laboratory (LLNL). In this role, he is responsible for formulating LLNL's large-scale computing strategy and overseeing its implementation. His position requires frequent interaction with high performance computing (HPC) leaders and he oversees several collaborations with the HPC industry as well as academia. He is also the LLNL principal point of contact for the Scientific Discovery through Advanced Computing (SciDAC) program's Institute for Sustained Performance, Energy and Resilience (SUPER), for which he leads the resilience thrust.

Prior to becoming CTO for LC, Bronis led several research projects in LLNL's Center for Applied Scientific Computing (CASC). Most recently, he led the Exascale Computing Technologies (ExaCT) project and co-led the Advanced Simulation and Computing (ASC) program's Application Development Environment and Performance Team (ADEPT). ADEPT is responsible for the development environment, including compilers, tools and run time systems, on LLNL's large-scale systems. ExaCT explored several critical directions related to programming models, algorithms, performance, code correctness and resilience for future large scale systems. He currently continues his interests in these topics, particularly programming models, and serves as the Chair of the OpenMP Language Committee.

Bronis earned his Ph.D. in Computer Science from the University of Virginia in 1998, and he joined CASC in July 1998. His dissertation investigated shared memory coherence based on isotach logical time systems. His research has covered a wide range of topics, including applications of data mining techniques to performance analysis and modeling including performance modeling through non-linear regression techniques (i.e., artificial neural networks and piecewise polynomial regression), investigations into mechanisms and tools to improve memory performance, a variety of optimization techniques and tools for MPI, and several issues with OpenMP, including its memory model and tool support.

Throughout his career, Bronis has won several awards, including the prestigious Gordon Bell Prize in 2005 and 2006, as well as an R&D 100 for his leadership of a team that developed a novel scalable debugging tool. He serves on the program committees of numerous conferences and workshops. He is a member of the ACM and the IEEE Computer Society.

Michael James

Michael is co-founder and Chief Architect of Advanced Technologies at Cerebras, the company that created the world’s largest and most powerful computer processor. Michael leads the effort to reimagine the algorithmic building blocks for the next generation of AI technologies. Prior to Cerebras, Michael was a Fellow at AMD, where he pioneered a technique of adaptive and self-healing circuits based on cellular automata that was applied toward distributed fault tolerant machines. Michael focuses his career on exploration at the intersection of natural phenomena, mathematics, and engineered machines.

Shimon Ben David

As WekaIO’s CTO, Mr Shimon Ben-David actively engages with customers and partners to track emerging trends and to bring actionable feedback to Engineering and Product Management, with a focus on Financials and Life science markets as well as AI/ML and GPU workloads. In his more than 6 years at WekaIO, he grew with leadership roles in both Support and Sales Engineering organizations. Prior to joining WekaIO he led the Support Services for Primary Data, XtremIO, and IBM XIV. Shimon met the leadership team of WekaIO when he managed IT at XIV, acquired by IBM in 2007.

Dirk Van Essendelft

Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory.  The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations.  Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry.  In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways.  Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.

Recent publications:

• Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.

Olivier Beaumont

Olivier Beaumont, Ph.D. holds a senior researcher position (Directeur de Recherche) at Inria since October 2008. He defended his PhD thesis in 1999 and his Habilitation in 2004. His main interests are in scheduling, load balancing, HPC and memory optimization and parallelization of training. He served as PC Chair (Algorithm Track) for many HPC conferences (SuperComputing, IPDPS, ICPP, HIPC,...) and he is acting as Associate Editor in Chief of JPDC (Journal of Parallel and Distributed Computing). He is the author of more than 90 papers in international journals and conferences.

Rob Schreiber

Rob Schreiber is a Distinguished Engineer at Cerebras Systems, Inc., where he works on architecture and programming of systems for accelerated training of deep neural networks. Schreiber’s research spans sequential and parallel algorithms for matrix computation, compiler optimization for parallel languages, and high performance computer design. With Moler and Gilbert, he developed the sparse matrix extension of Matlab.  He created the NAS CG parallel benchmark.  He was a designer of the High Performance Fortran language. Rob led the development at HP of the PICO system for synthesis of custom hardware accelerators.  He has help pioneer the exploitation of photonic signaling in processors and networks. He is an ACM Fellow, a SIAM Fellow, and was awarded, in 2012, the Career Prize from the SIAM Activity Group in Supercomputing.

Sorin Cheran

Sorin Cheran is an HPE Fellow and currently serves as vice president of HPE’s AI Strategy and Solutions Group which is responsible for the company’s global AI strategy.  Since 2007, Sorin has held positions including AI and Chief Architect in Hewlett Packard Labs and as a key member in the Hybrid IT Presales team in the High-Performance Computing (HPC) and AI Competency Center in Grenoble, France. Sorin’s drive, creativity, energetic leadership and spirit of collaboration consistently delivers outstanding business outcomes for HPE and its customers. He has nurtured and evangelized Artificial Intelligence within HPE, as well as externally with customers and partners. 

 is an HPE Fellow and currently serves as vice president of HPE’s AI Strategy and Solutions Group which is responsible for the company’s global AI strategy.  Since 2007, Sorin has held positions including AI and Chief Architect in Hewlett Packard Labs and as a key member in the Hybrid IT Presales team in the High-Performance Computing (HPC) and AI Competency Center in Grenoble, France. Sorin’s drive, creativity, energetic leadership and spirit of collaboration consistently delivers outstanding business outcomes for HPE and its customers. He has nurtured and evangelized Artificial Intelligence within HPE, as well as externally with customers and partners. 

Subhasish Mitra

Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. Prof. Mitra also holds the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system, and have inspired significant government and research initiatives in multiple countries. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx.

In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st century systems, enabling billions of dollars in cost savings.

With his students and collaborators, he demonstrated the first carbon nanotube computer. They also demonstrated the first 3D NanoSystem with computation immersed in data storage. These received wide recognition: cover of NATURE, Research Highlight to the US Congress by the NSF, and highlight as "important, scientific breakthrough" by global news organizations.

Prof. Mitra's honors include the Newton Technical Impact Award in EDA (test of time honor by ACM SIGDA and IEEE CEDA), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He has published award-winning papers at major venues such as the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, Symposium on VLSI Technology, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times "for being important to them." He is an ACM Fellow and an IEEE Fellow.